1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NFET devices or PFET devices. During the fabrication of complex integrated circuits, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions. The channel length of a transistor is generally considered to be the lateral distance between the source/drain regions.
As device dimensions have continued to shrink over recent years, it is becoming more challenging to accurately and repeatedly manufacture integrated circuit products that meet performance criteria established for such integrated circuit products. Typically, semiconductor devices are formed on discrete islands of semiconducting substrate, i.e., active regions that are defined in the substrate by isolation structures. For example, FIGS. 1 and 2 depict an illustrative prior art device 10 comprised of first and second cells (“Cell 1” and “Cell 2”). The cells are intended to be representative in nature. For example, in one illustrative example, Cell 1 may be a NAND circuit and Cell 2 may also be a NAND circuit. In another example, Cell 1 may be an inverter and Cell 2 may be a flip-flop.
With continuing reference to FIGS. 1 and 2, a plurality of spaced apart active regions 12PA, 12PB, 12NA and 12NB are defined in a semiconducting substrate by one or more isolation structures. A plurality of PFET devices 20P1-2 are formed in and above the active region 12PA and a plurality of PFET devices 20P3-4 are formed in and above the active region 12PB. The PFET devices comprise P-doped source/drain regions 32P, while the NFET devices 22N1-4 comprise N-doped source/drain regions 32N. In the depicted example, the various PFET and NFET devices share a common electrode structure 30 that extends across the separated active regions and the isolation region therebetween. For example, PFET transistor 20P1 and NFET transistor 22N1 share a common gate electrode structure 30 that extends across both of the active regions 12PA, 12NA and the isolation region between those two active regions. The structures 14 may be dummy gate structures that are provided in an attempt to improve dimensional accuracy when forming the gate structures 30 for the device 10.
FIG. 2 depicts another illustrative prior art device 50. The device comprises illustrative PFET devices 20P1 and 20P2 formed above spaced apart active regions. The device 50 also includes illustrative NFET transistors 22N1, 22N2 that are also formed above spaced apart active regions. FIG. 2 depicts an illustrative relatively high voltage power rail 40H that is conductively coupled to the illustrative source regions (“S”) of the PFET devices 20P1, 20P2 via illustrative contacts 52H. Also depicted in FIG. 2 is an illustrative relatively low voltage power rail 40L that is conductively coupled to the source regions of the NFET devices 22N1, 22N2 via illustrative contacts 52L.
With each new technology generation, all dimensions of the integrated circuit product are typically reduced. For example, as device dimensions are reduced, the lateral spacing 39 (see FIG. 1) between adjacent active regions, e.g., the lateral spacing 39 between the active regions 12PA and 12PB, also decreases. In some cases, the lateral spacing 39 may be as little as about 40 nm. As this lateral spacing decreases, there is an increased risk of creating short circuits between the two adjacent cells. Of course, one way to rectify this problem would be to simply increase the spacing between adjacent active regions. However, such an approach would be very costly in terms of the plot space on the device that is lost and would run counter to the trend in integrated circuit products of reducing the size of such products. Other techniques have been tried to alleviate this problem, e.g., a so-called Rx-tuck process, but such processes also tend to consume excessive amounts of chip plot space and may result in considerable device performance degradation.
The present disclosure is directed to a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.